cpldfit:  version P.20131013                        Xilinx Inc.
                                  Fitter Report
Design Name: ps2_seq_amjp                        Date: 12-14-2017, 10:04AM
Device Used: XC9572XL-5-PC44
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
38 /72  ( 53%) 111 /360  ( 31%) 67 /216 ( 31%)   36 /72  ( 50%) 6  /34  ( 18%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1          14/18       16/54       38/90       3/ 9
FB2           2/18       19/54        9/90       3/ 9
FB3           7/18       16/54       32/90       0/ 9
FB4          15/18       16/54       32/90       0/ 7
             -----       -----       -----      -----    
             38/72       67/216     111/360      6/34 

* - Resource is exhausted

** Global Control Resources **

Signal 'Clk' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    3           3    |  I/O              :     4      28
Output        :    2           2    |  GCK/IO           :     1       3
Bidirectional :    0           0    |  GTS/IO           :     0       2
GCK           :    1           1    |  GSR/IO           :     1       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total      6           6

** Power Data **

There are 38 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
   use the default filename of 'ps2_seq_amjp.ise'.
*************************  Summary of Mapped Logic  ************************

** 2 Outputs **

Signal                                  Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                                    Pts   Inps          No.  Type    Use     Mode Rate State
y                                       1     2     FB2_2   35   I/O     O       STD  FAST 
RS_TxOut                                8     17    FB2_17  44   I/O     O       STD  FAST SET

** 36 Buried Nodes **

Signal                                  Total Total Loc     Pwr  Reg Init
Name                                    Pts   Inps          Mode State
XLXI_3/Cnt<0>                           1     3     FB1_5   STD  RESET
XLXI_3/sReg<9>                          2     8     FB1_6   STD  SET
XLXI_3/Cnt<1>                           2     4     FB1_7   STD  RESET
XLXI_3/sReg<8>                          3     9     FB1_8   STD  RESET
XLXI_3/sReg<7>                          3     9     FB1_9   STD  RESET
XLXI_3/sReg<6>                          3     9     FB1_10  STD  RESET
XLXI_3/sReg<5>                          3     9     FB1_11  STD  RESET
XLXI_3/sReg<4>                          3     9     FB1_12  STD  RESET
XLXI_3/sReg<3>                          3     9     FB1_13  STD  RESET
XLXI_3/sReg<2>                          3     9     FB1_14  STD  RESET
XLXI_3/sReg<1>                          3     9     FB1_15  STD  RESET
XLXI_3/iBusy                            3     16    FB1_16  STD  RESET
XLXI_3/Cnt<3>                           3     6     FB1_17  STD  RESET
XLXI_3/Cnt<2>                           3     5     FB1_18  STD  RESET
XLXI_2/state_FSM_FFd4                   10    14    FB3_1   STD  RESET
XLXN_35                                 1     5     FB3_12  STD  RESET
XLXI_1/Cnt<2>/XLXI_1/Cnt<2>_RSTF__$INT  1     2     FB3_13  STD  
XLXI_79/state_FSM_FFd1                  2     5     FB3_14  STD  RESET
XLXI_2/state_FSM_FFd1                   5     14    FB3_15  STD  RESET
XLXI_2/state_FSM_FFd2                   6     14    FB3_17  STD  RESET
XLXI_2/state_FSM_FFd3                   7     14    FB3_18  STD  RESET
XLXN_2                                  1     4     FB4_4   STD  RESET
XLXN_1<7>                               2     2     FB4_5   STD  RESET
XLXN_1<6>                               2     2     FB4_6   STD  RESET
XLXN_1<5>                               2     2     FB4_7   STD  RESET
XLXN_1<4>                               2     2     FB4_8   STD  RESET
XLXN_1<3>                               2     2     FB4_9   STD  RESET
XLXN_1<2>                               2     2     FB4_10  STD  RESET
XLXN_1<1>                               2     2     FB4_11  STD  RESET
XLXN_1<0>                               2     2     FB4_12  STD  RESET
XLXI_1/reg10b<9>                        2     2     FB4_13  STD  RESET
XLXI_1/reg10b<8>                        2     2     FB4_14  STD  RESET
XLXI_1/Cnt<0>                           2     2     FB4_15  STD  RESET
XLXI_1/Cnt<3>                           3     5     FB4_16  STD  RESET
XLXI_1/Cnt<2>                           3     4     FB4_17  STD  RESET
XLXI_1/Cnt<1>                           3     3     FB4_18  STD  RESET

** 4 Inputs **

Signal                                  Loc     Pin  Pin     Pin     
Name                                            No.  Type    Use     
PS2_Data                                FB1_5   2    I/O     I
PS2_Clk                                 FB1_6   3    I/O     I
Clk                                     FB1_9   5    GCK/I/O GCK
Reset                                   FB2_9   39   GSR/I/O I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X            - Signal used as input to the macrocell logic.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               16/38
Number of signals used by logic mapping into function block:  16
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB1_1         (b)     
(unused)              0       0     0   5     FB1_2   1     I/O     
(unused)              0       0     0   5     FB1_3         (b)     
(unused)              0       0     0   5     FB1_4         (b)     
XLXI_3/Cnt<0>         1       0     0   4     FB1_5   2     I/O     I
XLXI_3/sReg<9>        2       0     0   3     FB1_6   3     I/O     I
XLXI_3/Cnt<1>         2       0     0   3     FB1_7         (b)     (b)
XLXI_3/sReg<8>        3       0     0   2     FB1_8   4     I/O     (b)
XLXI_3/sReg<7>        3       0     0   2     FB1_9   5     GCK/I/O GCK
XLXI_3/sReg<6>        3       0     0   2     FB1_10        (b)     (b)
XLXI_3/sReg<5>        3       0     0   2     FB1_11  6     GCK/I/O (b)
XLXI_3/sReg<4>        3       0     0   2     FB1_12        (b)     (b)
XLXI_3/sReg<3>        3       0     0   2     FB1_13        (b)     (b)
XLXI_3/sReg<2>        3       0     0   2     FB1_14  7     GCK/I/O (b)
XLXI_3/sReg<1>        3       0     0   2     FB1_15  8     I/O     (b)
XLXI_3/iBusy          3       0     0   2     FB1_16        (b)     (b)
XLXI_3/Cnt<3>         3       0     0   2     FB1_17  9     I/O     (b)
XLXI_3/Cnt<2>         3       0     0   2     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: Reset              7: XLXI_3/sReg<1>    12: XLXI_3/sReg<6> 
  2: XLXI_3/Cnt<0>      8: XLXI_3/sReg<2>    13: XLXI_3/sReg<7> 
  3: XLXI_3/Cnt<1>      9: XLXI_3/sReg<3>    14: XLXI_3/sReg<8> 
  4: XLXI_3/Cnt<2>     10: XLXI_3/sReg<4>    15: XLXI_3/sReg<9> 
  5: XLXI_3/Cnt<3>     11: XLXI_3/sReg<5>    16: XLXN_35 
  6: XLXI_3/iBusy     

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
XLXI_3/Cnt<0>        XX...X.................................. 3
XLXI_3/sReg<9>       XXXXXX........XX........................ 8
XLXI_3/Cnt<1>        XXX..X.................................. 4
XLXI_3/sReg<8>       XXXXXX.......XXX........................ 9
XLXI_3/sReg<7>       XXXXXX......XX.X........................ 9
XLXI_3/sReg<6>       XXXXXX.....XX..X........................ 9
XLXI_3/sReg<5>       XXXXXX....XX...X........................ 9
XLXI_3/sReg<4>       XXXXXX...XX....X........................ 9
XLXI_3/sReg<3>       XXXXXX..XX.....X........................ 9
XLXI_3/sReg<2>       XXXXXX.XX......X........................ 9
XLXI_3/sReg<1>       XXXXXXXX.......X........................ 9
XLXI_3/iBusy         XXXXXXXXXXXXXXXX........................ 16
XLXI_3/Cnt<3>        XXXXXX.................................. 6
XLXI_3/Cnt<2>        XXXX.X.................................. 5
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               19/35
Number of signals used by logic mapping into function block:  19
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB2_1         (b)     
y                     1       0     0   4     FB2_2   35    I/O     O
(unused)              0       0     0   5     FB2_3         (b)     
(unused)              0       0     0   5     FB2_4         (b)     
(unused)              0       0     0   5     FB2_5   36    I/O     
(unused)              0       0     0   5     FB2_6   37    I/O     
(unused)              0       0     0   5     FB2_7         (b)     
(unused)              0       0     0   5     FB2_8   38    I/O     
(unused)              0       0     0   5     FB2_9   39    GSR/I/O I
(unused)              0       0     0   5     FB2_10        (b)     
(unused)              0       0     0   5     FB2_11  40    GTS/I/O 
(unused)              0       0     0   5     FB2_12        (b)     
(unused)              0       0     0   5     FB2_13        (b)     
(unused)              0       0     0   5     FB2_14  42    GTS/I/O 
(unused)              0       0     0   5     FB2_15  43    I/O     
(unused)              0       0   \/2   3     FB2_16        (b)     (b)
RS_TxOut              8       3<-   0   0     FB2_17  44    I/O     O
(unused)              0       0   /\1   4     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: RS_TxOut                8: XLXI_3/Cnt<3>     14: XLXI_3/sReg<5> 
  2: Reset                   9: XLXI_3/iBusy      15: XLXI_3/sReg<6> 
  3: XLXI_2/state_FSM_FFd1  10: XLXI_3/sReg<1>    16: XLXI_3/sReg<7> 
  4: XLXI_2/state_FSM_FFd2  11: XLXI_3/sReg<2>    17: XLXI_3/sReg<8> 
  5: XLXI_3/Cnt<0>          12: XLXI_3/sReg<3>    18: XLXI_3/sReg<9> 
  6: XLXI_3/Cnt<1>          13: XLXI_3/sReg<4>    19: XLXN_35 
  7: XLXI_3/Cnt<2>         

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
y                    ..XX.................................... 2
RS_TxOut             XX..XXXXXXXXXXXXXXX..................... 17
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               16/38
Number of signals used by logic mapping into function block:  16
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
XLXI_2/state_FSM_FFd4
                     10       7<- /\2   0     FB3_1         (b)     (b)
(unused)              0       0   /\5   0     FB3_2   11    I/O     (b)
(unused)              0       0   /\2   3     FB3_3         (b)     (b)
(unused)              0       0     0   5     FB3_4         (b)     
(unused)              0       0     0   5     FB3_5   12    I/O     
(unused)              0       0     0   5     FB3_6         (b)     
(unused)              0       0     0   5     FB3_7         (b)     
(unused)              0       0     0   5     FB3_8   13    I/O     
(unused)              0       0     0   5     FB3_9   14    I/O     
(unused)              0       0     0   5     FB3_10        (b)     
(unused)              0       0     0   5     FB3_11  18    I/O     
XLXN_35               1       0     0   4     FB3_12        (b)     (b)
XLXI_1/Cnt<2>/XLXI_1/Cnt<2>_RSTF__$INT
                      1       0     0   4     FB3_13        (b)     (b)
XLXI_79/state_FSM_FFd1
                      2       0     0   3     FB3_14  19    I/O     (b)
XLXI_2/state_FSM_FFd1
                      5       0     0   0     FB3_15  20    I/O     (b)
(unused)              0       0   \/1   4     FB3_16  24    I/O     (b)
XLXI_2/state_FSM_FFd2
                      6       1<-   0   0     FB3_17  22    I/O     (b)
XLXI_2/state_FSM_FFd3
                      7       2<-   0   0     FB3_18        (b)     (b)

Signals Used by Logic in Function Block
  1: Reset                    7: XLXN_1<0>         12: XLXN_1<5> 
  2: XLXI_2/state_FSM_FFd1    8: XLXN_1<1>         13: XLXN_1<6> 
  3: XLXI_2/state_FSM_FFd2    9: XLXN_1<2>         14: XLXN_1<7> 
  4: XLXI_2/state_FSM_FFd3   10: XLXN_1<3>         15: XLXN_2 
  5: XLXI_2/state_FSM_FFd4   11: XLXN_1<4>         16: XLXN_35 
  6: XLXI_79/state_FSM_FFd1 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
XLXI_2/state_FSM_FFd4 
                     XXXXX.XXXXXXXXX......................... 14
XLXN_35              XXX..X.........X........................ 5
XLXI_1/Cnt<2>/XLXI_1/Cnt<2>_RSTF__$INT 
                     X.............X......................... 2
XLXI_79/state_FSM_FFd1 
                     XXX..X.........X........................ 5
XLXI_2/state_FSM_FFd1 
                     XXXXX.XXXXXXXXX......................... 14
XLXI_2/state_FSM_FFd2 
                     XXXXX.XXXXXXXXX......................... 14
XLXI_2/state_FSM_FFd3 
                     XXXXX.XXXXXXXXX......................... 14
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               16/38
Number of signals used by logic mapping into function block:  16
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB4_1         (b)     
(unused)              0       0     0   5     FB4_2   25    I/O     
(unused)              0       0     0   5     FB4_3         (b)     
XLXN_2                1       0     0   4     FB4_4         (b)     (b)
XLXN_1<7>             2       0     0   3     FB4_5   26    I/O     (b)
XLXN_1<6>             2       0     0   3     FB4_6         (b)     (b)
XLXN_1<5>             2       0     0   3     FB4_7         (b)     (b)
XLXN_1<4>             2       0     0   3     FB4_8   27    I/O     (b)
XLXN_1<3>             2       0     0   3     FB4_9         (b)     (b)
XLXN_1<2>             2       0     0   3     FB4_10        (b)     (b)
XLXN_1<1>             2       0     0   3     FB4_11  28    I/O     (b)
XLXN_1<0>             2       0     0   3     FB4_12        (b)     (b)
XLXI_1/reg10b<9>      2       0     0   3     FB4_13        (b)     (b)
XLXI_1/reg10b<8>      2       0     0   3     FB4_14  29    I/O     (b)
XLXI_1/Cnt<0>         2       0     0   3     FB4_15  33    I/O     (b)
XLXI_1/Cnt<3>         3       0     0   2     FB4_16        (b)     (b)
XLXI_1/Cnt<2>         3       0     0   2     FB4_17  34    I/O     (b)
XLXI_1/Cnt<1>         3       0     0   2     FB4_18        (b)     (b)

Signals Used by Logic in Function Block
  1: PS2_Clk                                  7: XLXI_1/Cnt<3>     12: XLXN_1<3> 
  2: PS2_Data                                 8: XLXI_1/reg10b<8>  13: XLXN_1<4> 
  3: XLXI_1/Cnt<0>                            9: XLXI_1/reg10b<9>  14: XLXN_1<5> 
  4: XLXI_1/Cnt<1>                           10: XLXN_1<1>         15: XLXN_1<6> 
  5: XLXI_1/Cnt<2>                           11: XLXN_1<2>         16: XLXN_1<7> 
  6: XLXI_1/Cnt<2>/XLXI_1/Cnt<2>_RSTF__$INT 

Signal                        1         2         3         4 FB
Name                0----+----0----+----0----+----0----+----0 Inputs
XLXN_2               ..XXX.X................................. 4
XLXN_1<7>            X......X................................ 2
XLXN_1<6>            X..............X........................ 2
XLXN_1<5>            X.............X......................... 2
XLXN_1<4>            X............X.......................... 2
XLXN_1<3>            X...........X........................... 2
XLXN_1<2>            X..........X............................ 2
XLXN_1<1>            X.........X............................. 2
XLXN_1<0>            X........X.............................. 2
XLXI_1/reg10b<9>     XX...................................... 2
XLXI_1/reg10b<8>     X.......X............................... 2
XLXI_1/Cnt<0>        X....X.................................. 2
XLXI_1/Cnt<3>        X.XXXX.................................. 5
XLXI_1/Cnt<2>        X.XX.X.................................. 4
XLXI_1/Cnt<1>        X.X..X.................................. 3
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********











FDCPE_RS_TxOut: FDCPE port map (RS_TxOut,RS_TxOut_D,Clk,'0','0');
RS_TxOut_D <= ((Reset)
	OR (XLXI_3/iBusy AND RS_TxOut AND NOT XLXI_3/Cnt(3))
	OR (XLXI_3/iBusy AND XLXI_3/sReg(1) AND XLXI_3/Cnt(0) AND 
	XLXI_3/Cnt(1) AND XLXI_3/Cnt(2) AND XLXI_3/Cnt(3))
	OR (XLXI_3/iBusy AND RS_TxOut AND NOT XLXI_3/Cnt(0))
	OR (XLXI_3/iBusy AND RS_TxOut AND NOT XLXI_3/Cnt(1))
	OR (XLXI_3/iBusy AND RS_TxOut AND NOT XLXI_3/Cnt(2))
	OR (NOT XLXI_3/iBusy AND RS_TxOut AND NOT XLXN_35)
	OR (XLXI_3/iBusy AND NOT XLXI_3/sReg(2) AND NOT XLXI_3/sReg(3) AND 
	NOT XLXI_3/sReg(4) AND NOT XLXI_3/sReg(5) AND NOT XLXI_3/sReg(6) AND NOT XLXI_3/sReg(7) AND 
	NOT XLXI_3/sReg(8) AND NOT XLXI_3/sReg(9) AND RS_TxOut));

FTCPE_XLXI_1/Cnt0: FTCPE port map (XLXI_1/Cnt(0),'1',NOT PS2_Clk,NOT XLXI_1/Cnt(2)/XLXI_1/Cnt(2)_RSTF__$INT,'0');

FTCPE_XLXI_1/Cnt1: FTCPE port map (XLXI_1/Cnt(1),XLXI_1/Cnt(0),NOT PS2_Clk,NOT XLXI_1/Cnt(2)/XLXI_1/Cnt(2)_RSTF__$INT,'0');

FTCPE_XLXI_1/Cnt2: FTCPE port map (XLXI_1/Cnt(2),XLXI_1/Cnt_T(2),NOT PS2_Clk,NOT XLXI_1/Cnt(2)/XLXI_1/Cnt(2)_RSTF__$INT,'0');
XLXI_1/Cnt_T(2) <= (XLXI_1/Cnt(0) AND XLXI_1/Cnt(1));


XLXI_1/Cnt(2)/XLXI_1/Cnt(2)_RSTF__$INT <= (NOT Reset AND NOT XLXN_2);

FTCPE_XLXI_1/Cnt3: FTCPE port map (XLXI_1/Cnt(3),XLXI_1/Cnt_T(3),NOT PS2_Clk,NOT XLXI_1/Cnt(2)/XLXI_1/Cnt(2)_RSTF__$INT,'0');
XLXI_1/Cnt_T(3) <= (XLXI_1/Cnt(0) AND XLXI_1/Cnt(1) AND XLXI_1/Cnt(2));

FDCPE_XLXI_1/reg10b8: FDCPE port map (XLXI_1/reg10b(8),XLXI_1/reg10b(9),NOT PS2_Clk,'0','0');

FDCPE_XLXI_1/reg10b9: FDCPE port map (XLXI_1/reg10b(9),PS2_Data,NOT PS2_Clk,'0','0');

FDCPE_XLXI_2/state_FSM_FFd1: FDCPE port map (XLXI_2/state_FSM_FFd1,XLXI_2/state_FSM_FFd1_D,Clk,'0','0');
XLXI_2/state_FSM_FFd1_D <= ((NOT Reset AND XLXI_2/state_FSM_FFd1 AND NOT XLXN_2)
	OR (NOT Reset AND XLXI_2/state_FSM_FFd4 AND 
	XLXI_2/state_FSM_FFd1 AND XLXN_1(0) AND XLXN_1(6) AND NOT XLXN_1(1) AND XLXN_1(3) AND 
	NOT XLXN_1(7) AND XLXN_1(2) AND NOT XLXN_1(4) AND NOT XLXN_1(5))
	OR (NOT Reset AND XLXI_2/state_FSM_FFd3 AND 
	NOT XLXI_2/state_FSM_FFd4 AND XLXI_2/state_FSM_FFd1 AND NOT XLXN_1(0) AND XLXN_1(6) AND 
	NOT XLXN_1(1) AND NOT XLXN_1(3) AND XLXN_1(7) AND NOT XLXN_1(2) AND XLXN_1(4) AND 
	XLXN_1(5))
	OR (NOT Reset AND XLXI_2/state_FSM_FFd3 AND 
	XLXI_2/state_FSM_FFd4 AND XLXI_2/state_FSM_FFd2 AND NOT XLXN_1(0) AND XLXN_1(6) AND 
	NOT XLXN_1(1) AND XLXN_2 AND NOT XLXN_1(3) AND XLXN_1(7) AND NOT XLXN_1(2) AND 
	XLXN_1(4) AND XLXN_1(5))
	OR (NOT Reset AND NOT XLXI_2/state_FSM_FFd3 AND 
	NOT XLXI_2/state_FSM_FFd4 AND XLXI_2/state_FSM_FFd1 AND NOT XLXI_2/state_FSM_FFd2 AND 
	XLXN_1(0) AND NOT XLXN_1(6) AND XLXN_1(1) AND XLXN_1(3) AND NOT XLXN_1(7) AND 
	NOT XLXN_1(2) AND XLXN_1(4) AND XLXN_1(5)));

FDCPE_XLXI_2/state_FSM_FFd2: FDCPE port map (XLXI_2/state_FSM_FFd2,XLXI_2/state_FSM_FFd2_D,Clk,'0','0');
XLXI_2/state_FSM_FFd2_D <= ((NOT Reset AND XLXI_2/state_FSM_FFd3 AND 
	XLXI_2/state_FSM_FFd4 AND NOT XLXI_2/state_FSM_FFd1 AND NOT XLXI_2/state_FSM_FFd2 AND 
	NOT XLXN_1(0) AND NOT XLXN_1(6) AND XLXN_1(1) AND XLXN_2 AND XLXN_1(3) AND 
	NOT XLXN_1(7) AND NOT XLXN_1(2) AND XLXN_1(4) AND XLXN_1(5))
	OR (NOT Reset AND XLXI_2/state_FSM_FFd2 AND NOT XLXN_2)
	OR (NOT Reset AND XLXI_2/state_FSM_FFd3 AND 
	NOT XLXI_2/state_FSM_FFd4 AND XLXI_2/state_FSM_FFd2 AND XLXN_1(0) AND NOT XLXN_1(6) AND 
	XLXN_1(1) AND XLXN_1(3) AND NOT XLXN_1(7) AND NOT XLXN_1(2) AND XLXN_1(4) AND 
	XLXN_1(5))
	OR (NOT Reset AND NOT XLXI_2/state_FSM_FFd3 AND 
	XLXI_2/state_FSM_FFd4 AND XLXI_2/state_FSM_FFd2 AND NOT XLXN_1(0) AND NOT XLXN_1(6) AND 
	XLXN_1(1) AND XLXN_1(3) AND NOT XLXN_1(7) AND NOT XLXN_1(2) AND XLXN_1(4) AND 
	XLXN_1(5))
	OR (NOT Reset AND XLXI_2/state_FSM_FFd3 AND 
	XLXI_2/state_FSM_FFd4 AND XLXI_2/state_FSM_FFd1 AND XLXN_1(0) AND XLXN_1(6) AND 
	NOT XLXN_1(1) AND XLXN_2 AND XLXN_1(3) AND NOT XLXN_1(7) AND XLXN_1(2) AND 
	NOT XLXN_1(4) AND NOT XLXN_1(5))
	OR (NOT Reset AND NOT XLXI_2/state_FSM_FFd3 AND 
	NOT XLXI_2/state_FSM_FFd4 AND NOT XLXI_2/state_FSM_FFd1 AND XLXI_2/state_FSM_FFd2 AND 
	NOT XLXN_1(0) AND XLXN_1(6) AND NOT XLXN_1(1) AND NOT XLXN_1(3) AND XLXN_1(7) AND 
	NOT XLXN_1(2) AND XLXN_1(4) AND XLXN_1(5)));

FDCPE_XLXI_2/state_FSM_FFd3: FDCPE port map (XLXI_2/state_FSM_FFd3,XLXI_2/state_FSM_FFd3_D,Clk,'0','0');
XLXI_2/state_FSM_FFd3_D <= ((NOT Reset AND NOT XLXI_2/state_FSM_FFd3 AND 
	XLXI_2/state_FSM_FFd4 AND XLXI_2/state_FSM_FFd1 AND XLXN_1(0) AND XLXN_1(6) AND 
	NOT XLXN_1(1) AND XLXN_2 AND XLXN_1(3) AND NOT XLXN_1(7) AND XLXN_1(2) AND 
	NOT XLXN_1(4) AND NOT XLXN_1(5))
	OR (NOT Reset AND NOT XLXI_2/state_FSM_FFd3 AND 
	XLXI_2/state_FSM_FFd4 AND NOT XLXI_2/state_FSM_FFd1 AND NOT XLXI_2/state_FSM_FFd2 AND 
	NOT XLXN_1(0) AND XLXN_1(6) AND NOT XLXN_1(1) AND XLXN_2 AND NOT XLXN_1(3) AND 
	XLXN_1(7) AND NOT XLXN_1(2) AND XLXN_1(4) AND XLXN_1(5))
	OR (NOT Reset AND XLXI_2/state_FSM_FFd3 AND NOT XLXN_2)
	OR (NOT Reset AND XLXI_2/state_FSM_FFd3 AND 
	NOT XLXI_2/state_FSM_FFd4 AND XLXI_2/state_FSM_FFd1 AND NOT XLXN_1(0) AND XLXN_1(6) AND 
	NOT XLXN_1(1) AND NOT XLXN_1(3) AND XLXN_1(7) AND NOT XLXN_1(2) AND XLXN_1(4) AND 
	XLXN_1(5))
	OR (NOT Reset AND XLXI_2/state_FSM_FFd3 AND 
	NOT XLXI_2/state_FSM_FFd4 AND XLXI_2/state_FSM_FFd2 AND XLXN_1(0) AND NOT XLXN_1(6) AND 
	XLXN_1(1) AND XLXN_1(3) AND NOT XLXN_1(7) AND NOT XLXN_1(2) AND XLXN_1(4) AND 
	XLXN_1(5))
	OR (NOT Reset AND XLXI_2/state_FSM_FFd3 AND 
	NOT XLXI_2/state_FSM_FFd4 AND NOT XLXI_2/state_FSM_FFd1 AND NOT XLXI_2/state_FSM_FFd2 AND 
	NOT XLXN_1(0) AND NOT XLXN_1(6) AND NOT XLXN_1(1) AND XLXN_1(3) AND NOT XLXN_1(7) AND 
	XLXN_1(2) AND XLXN_1(4) AND NOT XLXN_1(5))
	OR (NOT Reset AND NOT XLXI_2/state_FSM_FFd3 AND 
	XLXI_2/state_FSM_FFd4 AND XLXI_2/state_FSM_FFd2 AND NOT XLXN_1(0) AND NOT XLXN_1(6) AND 
	XLXN_1(1) AND XLXN_2 AND XLXN_1(3) AND NOT XLXN_1(7) AND NOT XLXN_1(2) AND 
	XLXN_1(4) AND XLXN_1(5)));

FDCPE_XLXI_2/state_FSM_FFd4: FDCPE port map (XLXI_2/state_FSM_FFd4,XLXI_2/state_FSM_FFd4_D,Clk,'0','0');
XLXI_2/state_FSM_FFd4_D <= ((EXP13_.EXP)
	OR (NOT Reset AND XLXI_2/state_FSM_FFd3 AND 
	NOT XLXI_2/state_FSM_FFd4 AND XLXI_2/state_FSM_FFd1 AND NOT XLXN_1(0) AND XLXN_1(6) AND 
	NOT XLXN_1(1) AND XLXN_2 AND NOT XLXN_1(3) AND XLXN_1(7) AND NOT XLXN_1(2) AND 
	XLXN_1(4) AND XLXN_1(5))
	OR (NOT Reset AND XLXI_2/state_FSM_FFd3 AND 
	NOT XLXI_2/state_FSM_FFd4 AND XLXI_2/state_FSM_FFd2 AND XLXN_1(0) AND NOT XLXN_1(6) AND 
	XLXN_1(1) AND XLXN_2 AND XLXN_1(3) AND NOT XLXN_1(7) AND NOT XLXN_1(2) AND 
	XLXN_1(4) AND XLXN_1(5))
	OR (NOT Reset AND XLXI_2/state_FSM_FFd3 AND 
	NOT XLXI_2/state_FSM_FFd4 AND XLXI_2/state_FSM_FFd2 AND NOT XLXN_1(0) AND NOT XLXN_1(6) AND 
	NOT XLXN_1(1) AND XLXN_2 AND XLXN_1(3) AND NOT XLXN_1(7) AND XLXN_1(2) AND 
	XLXN_1(4) AND NOT XLXN_1(5))
	OR (NOT Reset AND XLXI_2/state_FSM_FFd3 AND 
	NOT XLXI_2/state_FSM_FFd1 AND NOT XLXI_2/state_FSM_FFd2 AND NOT XLXN_1(0) AND NOT XLXN_1(6) AND 
	NOT XLXN_1(1) AND XLXN_2 AND XLXN_1(3) AND NOT XLXN_1(7) AND XLXN_1(2) AND 
	XLXN_1(4) AND NOT XLXN_1(5))
	OR (NOT Reset AND NOT XLXI_2/state_FSM_FFd4 AND 
	NOT XLXI_2/state_FSM_FFd1 AND NOT XLXI_2/state_FSM_FFd2 AND NOT XLXN_1(0) AND NOT XLXN_1(6) AND 
	NOT XLXN_1(1) AND XLXN_2 AND XLXN_1(3) AND NOT XLXN_1(7) AND XLXN_1(2) AND 
	XLXN_1(4) AND NOT XLXN_1(5))
	OR (NOT Reset AND XLXI_2/state_FSM_FFd4 AND NOT XLXN_2)
	OR (NOT Reset AND NOT XLXI_2/state_FSM_FFd3 AND 
	XLXI_2/state_FSM_FFd4 AND XLXI_2/state_FSM_FFd1 AND NOT XLXN_1(0) AND NOT XLXN_1(6) AND 
	NOT XLXN_1(1) AND XLXN_1(3) AND NOT XLXN_1(7) AND XLXN_1(2) AND XLXN_1(4) AND 
	NOT XLXN_1(5))
	OR (NOT Reset AND XLXI_2/state_FSM_FFd1 AND 
	XLXI_2/state_FSM_FFd2 AND NOT XLXN_1(0) AND NOT XLXN_1(6) AND NOT XLXN_1(1) AND XLXN_2 AND 
	XLXN_1(3) AND NOT XLXN_1(7) AND XLXN_1(2) AND XLXN_1(4) AND NOT XLXN_1(5)));

FDCPE_XLXI_3/Cnt0: FDCPE port map (XLXI_3/Cnt(0),XLXI_3/Cnt_D(0),Clk,'0','0');
XLXI_3/Cnt_D(0) <= (XLXI_3/iBusy AND NOT Reset AND NOT XLXI_3/Cnt(0));

FDCPE_XLXI_3/Cnt1: FDCPE port map (XLXI_3/Cnt(1),XLXI_3/Cnt_D(1),Clk,'0','0');
XLXI_3/Cnt_D(1) <= ((XLXI_3/iBusy AND NOT Reset AND XLXI_3/Cnt(0) AND 
	NOT XLXI_3/Cnt(1))
	OR (XLXI_3/iBusy AND NOT Reset AND NOT XLXI_3/Cnt(0) AND 
	XLXI_3/Cnt(1)));

FDCPE_XLXI_3/Cnt2: FDCPE port map (XLXI_3/Cnt(2),XLXI_3/Cnt_D(2),Clk,'0','0');
XLXI_3/Cnt_D(2) <= ((XLXI_3/iBusy AND NOT Reset AND NOT XLXI_3/Cnt(0) AND 
	XLXI_3/Cnt(2))
	OR (XLXI_3/iBusy AND NOT Reset AND NOT XLXI_3/Cnt(1) AND 
	XLXI_3/Cnt(2))
	OR (XLXI_3/iBusy AND NOT Reset AND XLXI_3/Cnt(0) AND 
	XLXI_3/Cnt(1) AND NOT XLXI_3/Cnt(2)));

FTCPE_XLXI_3/Cnt3: FTCPE port map (XLXI_3/Cnt(3),XLXI_3/Cnt_T(3),Clk,'0','0');
XLXI_3/Cnt_T(3) <= ((NOT XLXI_3/iBusy AND XLXI_3/Cnt(3))
	OR (Reset AND XLXI_3/Cnt(3))
	OR (XLXI_3/iBusy AND NOT Reset AND XLXI_3/Cnt(0) AND 
	XLXI_3/Cnt(1) AND XLXI_3/Cnt(2)));

FDCPE_XLXI_3/iBusy: FDCPE port map (XLXI_3/iBusy,XLXI_3/iBusy_D,Clk,'0','0');
XLXI_3/iBusy_D <= ((Reset)
	OR (NOT XLXI_3/iBusy AND NOT XLXN_35)
	OR (NOT XLXI_3/sReg(1) AND NOT XLXI_3/sReg(2) AND NOT XLXI_3/sReg(3) AND 
	NOT XLXI_3/sReg(4) AND NOT XLXI_3/sReg(5) AND NOT XLXI_3/sReg(6) AND NOT XLXI_3/sReg(7) AND 
	NOT XLXI_3/sReg(8) AND NOT XLXI_3/sReg(9) AND XLXI_3/Cnt(0) AND XLXI_3/Cnt(1) AND 
	XLXI_3/Cnt(2) AND XLXI_3/Cnt(3)));

FTCPE_XLXI_3/sReg1: FTCPE port map (XLXI_3/sReg(1),XLXI_3/sReg_T(1),Clk,'0','0');
XLXI_3/sReg_T(1) <= ((NOT XLXI_3/iBusy AND NOT XLXI_3/sReg(1) AND NOT Reset AND XLXN_35)
	OR (XLXI_3/iBusy AND XLXI_3/sReg(1) AND NOT XLXI_3/sReg(2) AND 
	NOT Reset AND XLXI_3/Cnt(0) AND XLXI_3/Cnt(1) AND XLXI_3/Cnt(2) AND 
	XLXI_3/Cnt(3))
	OR (XLXI_3/iBusy AND NOT XLXI_3/sReg(1) AND XLXI_3/sReg(2) AND 
	NOT Reset AND XLXI_3/Cnt(0) AND XLXI_3/Cnt(1) AND XLXI_3/Cnt(2) AND 
	XLXI_3/Cnt(3)));

FTCPE_XLXI_3/sReg2: FTCPE port map (XLXI_3/sReg(2),XLXI_3/sReg_T(2),Clk,'0','0');
XLXI_3/sReg_T(2) <= ((NOT XLXI_3/iBusy AND NOT XLXI_3/sReg(2) AND NOT Reset AND XLXN_35)
	OR (XLXI_3/iBusy AND XLXI_3/sReg(2) AND NOT XLXI_3/sReg(3) AND 
	NOT Reset AND XLXI_3/Cnt(0) AND XLXI_3/Cnt(1) AND XLXI_3/Cnt(2) AND 
	XLXI_3/Cnt(3))
	OR (XLXI_3/iBusy AND NOT XLXI_3/sReg(2) AND XLXI_3/sReg(3) AND 
	NOT Reset AND XLXI_3/Cnt(0) AND XLXI_3/Cnt(1) AND XLXI_3/Cnt(2) AND 
	XLXI_3/Cnt(3)));

FTCPE_XLXI_3/sReg3: FTCPE port map (XLXI_3/sReg(3),XLXI_3/sReg_T(3),Clk,'0','0');
XLXI_3/sReg_T(3) <= ((NOT XLXI_3/iBusy AND NOT XLXI_3/sReg(3) AND NOT Reset AND XLXN_35)
	OR (XLXI_3/iBusy AND XLXI_3/sReg(3) AND NOT XLXI_3/sReg(4) AND 
	NOT Reset AND XLXI_3/Cnt(0) AND XLXI_3/Cnt(1) AND XLXI_3/Cnt(2) AND 
	XLXI_3/Cnt(3))
	OR (XLXI_3/iBusy AND NOT XLXI_3/sReg(3) AND XLXI_3/sReg(4) AND 
	NOT Reset AND XLXI_3/Cnt(0) AND XLXI_3/Cnt(1) AND XLXI_3/Cnt(2) AND 
	XLXI_3/Cnt(3)));

FTCPE_XLXI_3/sReg4: FTCPE port map (XLXI_3/sReg(4),XLXI_3/sReg_T(4),Clk,'0','0');
XLXI_3/sReg_T(4) <= ((NOT XLXI_3/iBusy AND NOT XLXI_3/sReg(4) AND NOT Reset AND XLXN_35)
	OR (XLXI_3/iBusy AND XLXI_3/sReg(4) AND NOT XLXI_3/sReg(5) AND 
	NOT Reset AND XLXI_3/Cnt(0) AND XLXI_3/Cnt(1) AND XLXI_3/Cnt(2) AND 
	XLXI_3/Cnt(3))
	OR (XLXI_3/iBusy AND NOT XLXI_3/sReg(4) AND XLXI_3/sReg(5) AND 
	NOT Reset AND XLXI_3/Cnt(0) AND XLXI_3/Cnt(1) AND XLXI_3/Cnt(2) AND 
	XLXI_3/Cnt(3)));

FTCPE_XLXI_3/sReg5: FTCPE port map (XLXI_3/sReg(5),XLXI_3/sReg_T(5),Clk,'0','0');
XLXI_3/sReg_T(5) <= ((NOT XLXI_3/iBusy AND XLXI_3/sReg(5) AND NOT Reset AND XLXN_35)
	OR (XLXI_3/iBusy AND XLXI_3/sReg(5) AND NOT XLXI_3/sReg(6) AND 
	NOT Reset AND XLXI_3/Cnt(0) AND XLXI_3/Cnt(1) AND XLXI_3/Cnt(2) AND 
	XLXI_3/Cnt(3))
	OR (XLXI_3/iBusy AND NOT XLXI_3/sReg(5) AND XLXI_3/sReg(6) AND 
	NOT Reset AND XLXI_3/Cnt(0) AND XLXI_3/Cnt(1) AND XLXI_3/Cnt(2) AND 
	XLXI_3/Cnt(3)));

FTCPE_XLXI_3/sReg6: FTCPE port map (XLXI_3/sReg(6),XLXI_3/sReg_T(6),Clk,'0','0');
XLXI_3/sReg_T(6) <= ((NOT XLXI_3/iBusy AND XLXI_3/sReg(6) AND NOT Reset AND XLXN_35)
	OR (XLXI_3/iBusy AND XLXI_3/sReg(6) AND NOT XLXI_3/sReg(7) AND 
	NOT Reset AND XLXI_3/Cnt(0) AND XLXI_3/Cnt(1) AND XLXI_3/Cnt(2) AND 
	XLXI_3/Cnt(3))
	OR (XLXI_3/iBusy AND NOT XLXI_3/sReg(6) AND XLXI_3/sReg(7) AND 
	NOT Reset AND XLXI_3/Cnt(0) AND XLXI_3/Cnt(1) AND XLXI_3/Cnt(2) AND 
	XLXI_3/Cnt(3)));

FTCPE_XLXI_3/sReg7: FTCPE port map (XLXI_3/sReg(7),XLXI_3/sReg_T(7),Clk,'0','0');
XLXI_3/sReg_T(7) <= ((NOT XLXI_3/iBusy AND NOT XLXI_3/sReg(7) AND NOT Reset AND XLXN_35)
	OR (XLXI_3/iBusy AND XLXI_3/sReg(7) AND NOT XLXI_3/sReg(8) AND 
	NOT Reset AND XLXI_3/Cnt(0) AND XLXI_3/Cnt(1) AND XLXI_3/Cnt(2) AND 
	XLXI_3/Cnt(3))
	OR (XLXI_3/iBusy AND NOT XLXI_3/sReg(7) AND XLXI_3/sReg(8) AND 
	NOT Reset AND XLXI_3/Cnt(0) AND XLXI_3/Cnt(1) AND XLXI_3/Cnt(2) AND 
	XLXI_3/Cnt(3)));

FTCPE_XLXI_3/sReg8: FTCPE port map (XLXI_3/sReg(8),XLXI_3/sReg_T(8),Clk,'0','0');
XLXI_3/sReg_T(8) <= ((NOT XLXI_3/iBusy AND XLXI_3/sReg(8) AND NOT Reset AND XLXN_35)
	OR (XLXI_3/iBusy AND XLXI_3/sReg(8) AND NOT XLXI_3/sReg(9) AND 
	NOT Reset AND XLXI_3/Cnt(0) AND XLXI_3/Cnt(1) AND XLXI_3/Cnt(2) AND 
	XLXI_3/Cnt(3))
	OR (XLXI_3/iBusy AND NOT XLXI_3/sReg(8) AND XLXI_3/sReg(9) AND 
	NOT Reset AND XLXI_3/Cnt(0) AND XLXI_3/Cnt(1) AND XLXI_3/Cnt(2) AND 
	XLXI_3/Cnt(3)));

FTCPE_XLXI_3/sReg9: FTCPE port map (XLXI_3/sReg(9),XLXI_3/sReg_T(9),Clk,'0','0');
XLXI_3/sReg_T(9) <= ((NOT XLXI_3/iBusy AND NOT XLXI_3/sReg(9) AND NOT Reset AND XLXN_35)
	OR (XLXI_3/iBusy AND XLXI_3/sReg(9) AND NOT Reset AND 
	XLXI_3/Cnt(0) AND XLXI_3/Cnt(1) AND XLXI_3/Cnt(2) AND XLXI_3/Cnt(3)));

FDCPE_XLXI_79/state_FSM_FFd1: FDCPE port map (XLXI_79/state_FSM_FFd1,XLXI_79/state_FSM_FFd1_D,Clk,'0','0');
XLXI_79/state_FSM_FFd1_D <= ((NOT Reset AND XLXN_35)
	OR (NOT Reset AND XLXI_2/state_FSM_FFd1 AND 
	XLXI_2/state_FSM_FFd2 AND XLXI_79/state_FSM_FFd1));

FDCPE_XLXN_10: FDCPE port map (XLXN_1(0),XLXN_1(1),NOT PS2_Clk,'0','0');

FDCPE_XLXN_11: FDCPE port map (XLXN_1(1),XLXN_1(2),NOT PS2_Clk,'0','0');

FDCPE_XLXN_12: FDCPE port map (XLXN_1(2),XLXN_1(3),NOT PS2_Clk,'0','0');

FDCPE_XLXN_13: FDCPE port map (XLXN_1(3),XLXN_1(4),NOT PS2_Clk,'0','0');

FDCPE_XLXN_14: FDCPE port map (XLXN_1(4),XLXN_1(5),NOT PS2_Clk,'0','0');

FDCPE_XLXN_15: FDCPE port map (XLXN_1(5),XLXN_1(6),NOT PS2_Clk,'0','0');

FDCPE_XLXN_16: FDCPE port map (XLXN_1(6),XLXN_1(7),NOT PS2_Clk,'0','0');

FDCPE_XLXN_17: FDCPE port map (XLXN_1(7),XLXI_1/reg10b(8),NOT PS2_Clk,'0','0');

FDCPE_XLXN_2: FDCPE port map (XLXN_2,XLXN_2_D,Clk,'0','0');
XLXN_2_D <= (XLXI_1/Cnt(0) AND XLXI_1/Cnt(1) AND NOT XLXI_1/Cnt(2) AND 
	XLXI_1/Cnt(3));

FDCPE_XLXN_35: FDCPE port map (XLXN_35,XLXN_35_D,Clk,'0','0');
XLXN_35_D <= (NOT Reset AND XLXI_2/state_FSM_FFd1 AND 
	XLXI_2/state_FSM_FFd2 AND NOT XLXN_35 AND NOT XLXI_79/state_FSM_FFd1);


y <= (XLXI_2/state_FSM_FFd1 AND XLXI_2/state_FSM_FFd2);

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC9572XL-5-PC44


   --------------------------------  
  /6  5  4  3  2  1  44 43 42 41 40 \
 | 7                             39 | 
 | 8                             38 | 
 | 9                             37 | 
 | 10                            36 | 
 | 11        XC9572XL-5-PC44     35 | 
 | 12                            34 | 
 | 13                            33 | 
 | 14                            32 | 
 | 15                            31 | 
 | 16                            30 | 
 | 17                            29 | 
 \ 18 19 20 21 22 23 24 25 26 27 28 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 KPR                              23 GND                           
  2 PS2_Data                         24 KPR                           
  3 PS2_Clk                          25 KPR                           
  4 KPR                              26 KPR                           
  5 Clk                              27 KPR                           
  6 KPR                              28 KPR                           
  7 KPR                              29 KPR                           
  8 KPR                              30 TDO                           
  9 KPR                              31 GND                           
 10 GND                              32 VCC                           
 11 KPR                              33 KPR                           
 12 KPR                              34 KPR                           
 13 KPR                              35 y                             
 14 KPR                              36 KPR                           
 15 TDI                              37 KPR                           
 16 TMS                              38 KPR                           
 17 TCK                              39 Reset                         
 18 KPR                              40 KPR                           
 19 KPR                              41 VCC                           
 20 KPR                              42 KPR                           
 21 VCC                              43 KPR                           
 22 KPR                              44 RS_TxOut                      


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         KPR  = Unused I/O with weak keeper (leave unconnected)
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9572xl-5-PC44
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Set I/O Pin Termination                     : KEEPER
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 54
Pterm Limit                                 : 25