Timing Report

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Design Name ps2_seq_amjp
Device, Speed (SpeedFile Version) XC9572XL, -5 (3.0)
Date Created Thu Dec 14 08:49:49 2017
Created By Timing Report Generator: version P.20131013
Copyright Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

Summary

Performance Summary
Min. Clock Period 10.000 ns.
Max. Clock Frequency (fSYSTEM) 100.000 MHz.
Limited by Clock Pulse Width for PS2_Clk
Clock to Setup (tCYC) 6.300 ns.
Setup to Clock at the Pad (tSU) 4.400 ns.
Clock Pad to Output Pad Delay (tCO) 7.600 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 500.0 6.3 20 0


Constraint: TS1000

Description: PERIOD:PERIOD_Clk:500.000nS:HIGH:50.000000000:%
Path Requirement (ns) Delay (ns) Slack (ns)
XLXI_2/state_FSM_FFd1.Q to XLXI_2/state_FSM_FFd2.D 500.000 6.300 493.700
XLXI_2/state_FSM_FFd1.Q to XLXI_2/state_FSM_FFd3.D 500.000 6.300 493.700
XLXI_2/state_FSM_FFd1.Q to XLXI_2/state_FSM_FFd4.D 500.000 6.300 493.700



Number of constraints not met: 0

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
Clk 158.730 Limited by Cycle Time for Clk
PS2_Clk 100.000 Limited by Clock Pulse Width for PS2_Clk

Setup/Hold Times for Clocks

Setup/Hold Times for Clock Clk
Source Pad Setup to clk (edge) Hold to clk (edge)
Reset 4.400 0.000

Setup/Hold Times for Clock PS2_Clk
Source Pad Setup to clk (edge) Hold to clk (edge)
PS2_Data 1.700 0.000


Clock to Pad Timing

Clock Clk to Pad
Destination Pad Clock (edge) to Pad
y 7.600


Clock to Setup Times for Clocks

Clock to Setup for clock Clk
Source Destination Delay
XLXI_2/state_FSM_FFd1.Q XLXI_2/state_FSM_FFd2.D 6.300
XLXI_2/state_FSM_FFd1.Q XLXI_2/state_FSM_FFd3.D 6.300
XLXI_2/state_FSM_FFd1.Q XLXI_2/state_FSM_FFd4.D 6.300
XLXI_2/state_FSM_FFd2.Q XLXI_2/state_FSM_FFd2.D 6.300
XLXI_2/state_FSM_FFd2.Q XLXI_2/state_FSM_FFd3.D 6.300
XLXI_2/state_FSM_FFd2.Q XLXI_2/state_FSM_FFd4.D 6.300
XLXI_2/state_FSM_FFd3.Q XLXI_2/state_FSM_FFd2.D 6.300
XLXI_2/state_FSM_FFd3.Q XLXI_2/state_FSM_FFd3.D 6.300
XLXI_2/state_FSM_FFd3.Q XLXI_2/state_FSM_FFd4.D 6.300
XLXI_2/state_FSM_FFd4.Q XLXI_2/state_FSM_FFd2.D 6.300
XLXI_2/state_FSM_FFd4.Q XLXI_2/state_FSM_FFd3.D 6.300
XLXI_2/state_FSM_FFd4.Q XLXI_2/state_FSM_FFd4.D 6.300
XLXN_2.Q XLXI_2/state_FSM_FFd2.D 6.300
XLXN_2.Q XLXI_2/state_FSM_FFd3.D 6.300
XLXN_2.Q XLXI_2/state_FSM_FFd4.D 6.300
XLXI_2/state_FSM_FFd1.Q XLXI_2/state_FSM_FFd1.D 5.600
XLXI_2/state_FSM_FFd2.Q XLXI_2/state_FSM_FFd1.D 5.600
XLXI_2/state_FSM_FFd3.Q XLXI_2/state_FSM_FFd1.D 5.600
XLXI_2/state_FSM_FFd4.Q XLXI_2/state_FSM_FFd1.D 5.600
XLXN_2.Q XLXI_2/state_FSM_FFd1.D 5.600

Clock to Setup for clock PS2_Clk
Source Destination Delay
XLXI_1/Cnt<0>.Q XLXI_1/Cnt<1>.D 5.600
XLXI_1/Cnt<0>.Q XLXI_1/Cnt<2>.D 5.600
XLXI_1/Cnt<0>.Q XLXI_1/Cnt<3>.D 5.600
XLXI_1/Cnt<1>.Q XLXI_1/Cnt<2>.D 5.600
XLXI_1/Cnt<1>.Q XLXI_1/Cnt<3>.D 5.600
XLXI_1/Cnt<2>.Q XLXI_1/Cnt<3>.D 5.600
XLXI_1/reg10b<8>.Q XLXN_1<7>.D 5.600
XLXI_1/reg10b<9>.Q XLXI_1/reg10b<8>.D 5.600
XLXN_1<1>.Q XLXN_1<0>.D 5.600
XLXN_1<2>.Q XLXN_1<1>.D 5.600
XLXN_1<3>.Q XLXN_1<2>.D 5.600
XLXN_1<4>.Q XLXN_1<3>.D 5.600
XLXN_1<5>.Q XLXN_1<4>.D 5.600
XLXN_1<6>.Q XLXN_1<5>.D 5.600
XLXN_1<7>.Q XLXN_1<6>.D 5.600


Pad to Pad List

Source Pad Destination Pad Delay



Number of paths analyzed: 20
Number of Timing errors: 0
Analysis Completed: Thu Dec 14 08:49:49 2017